Modern memory architectures divide interfaces into shared command buses and independently routed bidirectional data lanes that face varying transit times. Because DDR3 and DDR4 use fly-by routing topologies, clock signals reach chained memory chips at staggered intervals rather than all at once. Hardware controllers resolve these discrepancies by calculating skew and shifting strobes relative to data bits. Implementations like LiteDRAM on FPGAs utilize phase-shifted clocks and specialized delay elements to enforce this precise synchronization.
Key points
Point-to-point data lanes require individual calibration because each independent path ex…: Point-to-point data lanes require individual calibration because each independent path experiences different physical signal delays.
Fly-by routing preserves overall signal integrity across chips but introduces clock skew…: Fly-by routing preserves overall signal integrity across chips but introduces clock skew that necessitates write-leveling adjustments during boot.
Physical layer controllers rely on custom hardware delays or phase-shifted clocks to main…: Physical layer controllers rely on custom hardware delays or phase-shifted clocks to maintain precise strobe and data alignments.
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This chapter explains what happens on the wires between the FPGA and the DRAM, and why a DRAM interface must be tuned at boot. It covers the signals, the strobes, the board topology, the leveling procedures, the termination and the reference voltages, then the clocks of the FPGA and the DFI interface between the controller and the PHY.
Each section ends with the part of LiteDRAM that implements the mechanism. The previous chapter, DRAM in a nutshell, explained the commands and the timings; Initialization and calibration gives the exact steps the BIOS runs.
A DRAM interface has two halves. The command and address half goes one way, from the controller to the DRAM, and is shared by every chip of a rank. The data half is bidirectional and split into byte lanes, each with its own strobe. The figure below shows the signals.
Signal | Direction | Role |
---|---|---|
CK, CK# | To the DRAM | Differential clock; commands are sampled on its rising edge |
CS#, RAS#, CAS#, WE# | To the DRAM | Command encoding; ACT_n added…
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