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Show HN: Fursoy – Out-of-order RV64IMAFDV core in SystemVerilog (Linux 6.6)

By · Published by Everything Blog

In short

Designed as a two-wide superscalar core, the processor integrates speculative execution features including a 128-entry reorder buffer and single-cycle branch recovery. It manages virtual memory demands through non-blocking L1 caches and a coherent hardware page table walker while booting mainline Linux 6.6.50. The complete system-on-chip incorporates custom SBI v2.0 firmware, interrupt controllers, and a 256 MiB DRAM interface. Standalone synthesis in a 45-nanometer cell library demonstrated that eight primary functional blocks met timing closure at 500 MHz.

Key points

  • The processor achieves full modern software compatibility by booting mainline Linux 6.6.5…: The processor achieves full modern software compatibility by booting mainline Linux 6.6.50 and a BusyBox userspace.
  • A balanced two-wide pipeline design manages instruction flow from fetch through retiremen…: A balanced two-wide pipeline design manages instruction flow from fetch through retirement across dedicated execution queues.
  • Synthesis evaluations on a 45-nanometer process confirm timing closure at 500 MHz across…: Synthesis evaluations on a 45-nanometer process confirm timing closure at 500 MHz across eight functional blocks totaling 111,019 cells.

Sources checked by our analysis pipeline: 1

A 64-bit Out-of-Order Superscalar RISC-V Processor (RV64IMAFDV + Zba + Zbb + Zicsr + Zifencei

) booting mainline Linux 6.6.50 and BusyBox userspace under Sv39 virtual memory.

Fursoy Slice-1 (fursoy_s1_core

/ fursoy_s1_soc

) is a clean-slate 64-bit out-of-order superscalar RISC-V processor implemented in SystemVerilog, featuring Sv39 demand paging, machine/supervisor/user privilege separation, cycle-exact hardware performance telemetry, and 500 MHz Nangate 45nm standard-cell synthesis closure across 8 core functional blocks.

- 2-Wide Superscalar OoO Core (

fursoy_s1_core

):- 2-wide fetch, decode, register rename, and in-order retirement (

M/S/U

privilege modes,medeleg

/mideleg

,WFI

,MRET

/SRET

). - 128-entry Reorder Buffer (

ROB_DEPTH = 128

) with 4-bit wrap-safe epoch tags and precise exception/interrupt flush recovery. - 160-entry Physical Integer Register File (

PRF_SIZE = 160

,128

speculative free-list entries) plus 8 branch checkpoints (NUM_CHECKPOINTS = 8

) for single-cycle speculative RAT rollback. - Dedicated issue queues: 32-entry Integer IQ (

INT_IQ_DEPTH = 32

), 32-entry Memory IQ (MEM_IQ_DEPTH = 32

), FP IQ (FPRF_SIZE = 64

), and decoupled 8-entry Vector IQ (VLEN = 256

,ELEN = 64

,48

vector physical registers). -…

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