Store forwarding functions smoothly when a subsequent read matches or sits completely inside the size of a prior write operation. In contrast, actions like modifying a single byte in a buffer before reading eight bytes trigger complete pipeline stalls across architectures. Benchmarks demonstrate that Intel Xeon and AMD EPYC chips suffer the sharpest penalties, surging from single-cycle matched loads to 19 and 14 cycles respectively. Developers can circumvent these delays by manipulating data directly in registers or ensuring matching read and write boundaries.
Key points
Processors stall when a read operation is wider than or only partially overlaps a precedi…: Processors stall when a read operation is wider than or only partially overlaps a preceding uncommitted store buffer.
Developers can avoid performance traps by manipulating values within registers rather tha…: Developers can avoid performance traps by manipulating values within registers rather than bouncing data through memory.
Aligning store and load sizes allows the mechanism to succeed and lets compilers eliminat…: Aligning store and load sizes allows the mechanism to succeed and lets compilers eliminate redundant reloads.
Sources checked by our analysis pipeline: 1
5 November 2026 · 2 min
A store does not go straight into the cache. Waiting for that write would stall the processor. It sits in a store buffer, and a later load can take its bytes from that buffer. That is store forwarding.
Forwarding works when the load is the same size as the store, or smaller and completely inside it. It fails when the load is wider than the store, or when the two ranges only partly overlap. The load then waits until the store has reached the cache.
Here is an example in C. We have a buffer, that might have received data previously. Yet one byte is overwritten, and we try to load 8 bytes. It will typically cause a store forwarding failure.
uint64_t reload_byte(char *p, unsigned char v) {
// Copy one byte from v into the buffer.
memcpy(p, &v, 1);
uint64_t w;
// Copy eight bytes from the buffer into w.
memcpy(&w, p, 8);
return w;
}
A 4-byte store followed by an 8-byte load would cause the same issue. So would an 8-byte…
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